Nortel-networks Circuit Card Bedienungsanleitung Seite 760
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Page 760 of 906 NTAK79 2.0 Mb PRI card
553-3001-211 Standard 3.00 August 2005
• jitter filtering
• use of an algorithm to detect crystal aging and to qualify clocking
information
Reference switchover
Switchover may occur in the case of reference degradation or reference
failure. When performance of the reference degrades to a point where the
system clock is no longer allowed to follow the timing signal, then the
reference will be said to be out of specification. If the reference being used is
out of specification and the other reference is still within specification, an
automatic switchover is initiated without software intervention. If both
references are out of specification, the clock controller provides holdover.
Autorecovery and chatter
If the software command “track to primary” is given, the clock controller
tracks to the primary reference and continuously monitors the quality of both
primary and secondary references. If the primary becomes out of
specification, the clock controller automatically tracks to secondary provided
that it is within specifications. On failure (both out of specification), the clock
controller enters the HOLDOVER mode and continuously monitors both
references. An automatic switchover is initiated to the reference that recovers
first. If the secondary recovers first, then the clock controller tracks to the
secondary, but switches over to the primary when the primary recovers. If the
primary recovers first, the clock controller tracks to the primary.
If the software command “track to secondary” is given, the clock controller
tracks to the secondary reference and continuously monitors the quality of
both primary and secondary references. If the secondary becomes out of
specification, the clock controller automatically tracks to primary provided
that it is within specifications. On failure (both out of spec.), the clock
controller enters the HOLDOVER mode and continuously monitors both
references. An automatic switchover is initiated to the reference that recovers
first. If the primary recovers first, then the clock controller tracks to the
primary, but switches over to the secondary whenever the secondary
recovers. If the secondary recovers first, then the clock controller tracks to the
secondary.
- Circuit Card 1
- Revision history 3
- Page 6 of 906 Contents 6
- Contents Page 9 of 906 9
- Page 10 of 906 Contents 10
- NT8D09 Analog Message Waiting 11
- Page 12 of 906 Contents 12
- Contents Page 13 of 906 13
- Page 14 of 906 Contents 14
- NTCK16 Generic Central Office 15
- NTDK20 Small System 15
- QPC513 Enhanced Serial Data 16
- Contents Page 17 of 906 17
- Page 18 of 906 Contents 18
- LIst of procedures 19
- About this document 21
- Applicable systems 22
- Intended audience 23
- Conventions 24
- Related information 25
- Line cards 28
- Overview Page 29 of 906 29
- Overview Page 33 of 906 33
- Page 34 of 906 Overview 34
- Figure 2 34
- Overview Page 35 of 906 35
- Page 36 of 906 Overview 36
- Figure 3 36
- DS-30X loop data format 36
- Analog line interface units 37
- Page 38 of 906 Overview 38
- Figure 4 38
- Overview Page 39 of 906 39
- Digital line interface units 40
- Overview Page 41 of 906 41
- Figure 5 41
- Analog line call operation 42
- Overview Page 43 of 906 43
- Figure 6 43
- Page 44 of 906 Overview 44
- Figure 7 44
- Overview Page 45 of 906 45
- Digital line call operation 46
- Lineside T1 call operation 46
- Overview Page 47 of 906 47
- Figure 8 47
- 553-AAA1116 48
- Overview Page 49 of 906 49
- Page 50 of 906 Overview 50
- Overview Page 53 of 906 53
- Page 56 of 906 Overview 56
- Voice frequency audio level 57
- Off-premise line protection 57
- Line protectors 57
- Line protection grounding 58
- Trunk cards 59
- Page 62 of 906 Overview 62
- Figure 10 62
- 553-6156 64
- Overview Page 65 of 906 65
- Page 66 of 906 Overview 66
- Overview Page 67 of 906 67
- Figure 12 67
- Page 68 of 906 Overview 68
- Figure 13 68
- Trunk interface unit 69
- Page 70 of 906 Overview 70
- Figure 14 70
- Overview Page 71 of 906 71
- Overview Page 77 of 906 77
- Page 78 of 906 Overview 78
- Circuit card installation 79
- Table 12 81
- Component Large System 81
- Precautions 84
- Figure 15 85
- Static discharge points 85
- Installing a circuit card 86
- 553-5002 87
- Acceptance tests 89
- Conference cards 90
- Digitone receiver cards 92
- Multifrequency sender cards 94
- Network cards 95
- Tone and digit switch cards 97
- Option settings 101
- Circuit card grid 102
- 553-5491 103
- ONP CLS OPX CLS 104
- TIMP: 600 ohms 600 ohms 104
- BIMP: 600 ohms 3COM2 104
- Trunk interface switches 107
- General purpose switches 107
- Ring ground switches 109
- NT5D12AA DDP card 111
- 553-7308 112
- 1 2 3 4 113
- NT6D42 Ringing Generator DC 114
- NT6D68 Core module backplane 117
- NT8D14 Universal Trunk card 119
- Jumper block 120
- Jumper strap 120
- Jumper pin 120
- NT8D15 E&M Trunk card 124
- NT8D17 Conference/TDS card 125
- NT8D21 Ringing Generator AC 126
- NT8D22 System Monitor 127
- For future use 132
- Figure 20 135
- NT8D72 DIP switch settings 135
- QPC414 Network card 137
- QPC441 3-Port Extender cards 138
- QPC471 Clock Controller card 144
- QPC775 Clock Controller card 152
- NT1R20 Off-Premise Station 157
- Analog Line card 157
- Physical description 158
- 553-6190 159
- Functional description 160
- Card interfaces 161
- Card control functions 162
- Electrical specifications 165
- Analog line interface 166
- Power requirements 167
- Ringer limitations 167
- Operation 168
- Incoming calls 169
- Outgoing calls 170
- Connector pin assignments 172
- 553-AAA1117 173
- Jumper strap settings 174
- Application 175
- 553-6191 176
- 553-AAA1118 178
- Other applications 179
- Transmission considerations 179
- NT4N39AA CP Pentium IV Card 183
- COM1 and COM2 ports 187
- USB port 189
- Front panel LED indicators 190
- Post 80 Debug LEDs (Optional) 191
- NT5D11 and NT5D14 Lineside T1 193
- Interface cards 193
- 553-6478 195
- 553-6476 198
- T1 interface circuit 200
- Signaling and control 200
- Environmental specifications 204
- Dip switch settings 205
- Figure 31 206
- Installation 210
- Cabling the lineside T1 card 213
- Figure 32 214
- I/O cable 217
- Figure 33 221
- 553-6481 221
- Terminal configuration 222
- Software configuration 222
- Description 225
- Login and password 227
- Basic commands 228
- Set Clearing 231
- Configuring parameters 232
- Alarm operation and reporting 236
- 553-AAA1120 243
- 553-AAA1121 243
- Applications 244
- Figure 37 245
- Figure 38 246
- Figure 39 247
- NT5D33 and NT5D34 Lineside E1 249
- Card connections 251
- Faceplate 251
- Figure 40 252
- NT5D33AB LEI card – faceplate 252
- Figure 41 253
- NT5D34AB LEI card – faceplate 253
- Figure 42 256
- LEI card – block diagram 256
- Overview 257
- E1 interface circuit 258
- ELEI additional functionality 260
- E1 Coding 265
- Figure 44 266
- Cabling the LEI card 274
- Software Configuration 281
- Login and Password 286
- Figure 46 287
- HELP (H, ?) screen 287
- Figure 49 296
- Figure 50 297
- Set Mode (S M): Table screen 297
- Table 99 on page 270 298
- Figure 52 301
- Figure 53 303
- Display Alarm (D A) screen 303
- Figure 54 304
- Display Status (D S) screen 304
- Figure 55 305
- Figure 56 306
- Display History (D H) screen 306
- Test 1: Local Loopback Test 307
- (1,2,3 or S to cancel): 307
- 553-1160 308
- 553-1161 309
- 553-1162 309
- Figure 63 311
- Figure 64 312
- Contents 313
- Introduction 313
- Configuration 318
- NT5D97 faceplate 321
- Figure 65 322
- Port definitions 326
- Cable requirements 328
- 553-7385 330
- NT8D7217 (A0617192) 331
- NTCK78AA (A0618294) 332
- NTCK79AA (A0618296) 333
- 553-7388 334
- 2.8, 4, 7 or 14 ft 335
- 553-7387 336
- Cable diagrams 337
- LED's 338
- Figure 75 342
- Dip switches for NT5D97AA/AB 342
- NT5D97AA/AB 345
- NT5D97AD DIP switch settings 347
- Figure 76 348
- Trunk 0 switches 349
- Trunk 1 switches for NT5D97AD 350
- NT5D97AD 351
- MSDL external card 352
- Architecture 353
- Reference 354
- Secondary 354
- Automatic clock recovery 355
- Automatic clock switching 356
- Clock configurations 356
- Figure 79 360
- Clock Controller – Option 2 360
- Figure 80 361
- Clock Controller – Option 3 361
- Figure 81 362
- Clock Controller – Option 4 362
- Configuring the NT5D97 365
- Testability and diagnostics 366
- NT5K21 XMFC/MFE card 369
- Signaling levels 370
- Forward and backward signals 370
- MFE signaling 372
- Sender and receiver mode 373
- Physical specifications 376
- NT6D70 SILC Line card 379
- Micro Controller Unit (MCU) 381
- IPE interface logic 382
- S/T interface logic 382
- NT6D71 UILC Line card 385
- U interface logic 387
- NT6D80 MSDL card 389
- Figure 82 391
- MSDL component layout 391
- 553-5431 391
- Figure 83 393
- MSDL block diagram 393
- Micro Processing Unit (MPU) 394
- Serial interface 394
- MSDL operations 395
- Figure 84 396
- MSDL functional block diagram 396
- 553-5433 396
- Engineering guidelines 397
- Card mix 398
- Address decoding 398
- Port specifications 398
- Implementation guidelines 402
- Figure 85 406
- MSDL switch setting example 406
- Installing the MSDL card 407
- Figure 86 409
- MSDL cabling 409
- 553-5845 409
- Cable installation 410
- I/O panel connections 411
- MSDL planning form 412
- Maintenance 413
- 553-5435 414
- DIS MSDL x to disable 415
- Maintaining the MSDL 416
- System controlled maintenance 416
- Replacing MSDL cards 421
- Symptoms and actions 422
- System disabled actions 423
- NT7D16 Data Access card 427
- Features 428
- Controls and indicators 429
- Dialing operations 430
- Figure 88 431
- Call Set-up abort 432
- Make Port Busy on loss of DTR 432
- Inactivity timeout 433
- Wire test mode 433
- Operating modes 435
- Figure 89 442
- DAC to modem connectivity 442
- Figure 90 445
- 553-AAA1126 445
- Figure 91 450
- DAC to Gateway connectivity 450
- Figure 92 451
- 553-AAA1127 451
- Figure 93 454
- DAC to Host connectivity 454
- Figure 94 458
- DAC to Terminal connectivity 458
- Mode selection baud rates 460
- Keyboard dialing 472
- Initiating conditions 473
- Call abort 474
- Autobaud 474
- Auto parity 475
- Dialing operation 475
- Primary commands 476
- Answer feature 480
- Ring Again 481
- Not in service 484
- No response from the system 484
- Hayes dialing 485
- Input requirements 486
- Result codes and messages 487
- Baud rate detection 488
- Parity detection 488
- S registers 490
- Reset Hayes parameters 493
- Outbound calls 495
- Inbound calls 495
- Off Line mode 496
- Specifications 497
- System parameters 498
- Operating parameters 498
- System database requirements 500
- Figure 95 501
- Figure 96 502
- Power supply 504
- Environmental 505
- Reliability 505
- Cabinet system 505
- Large System 506
- System compatibility 506
- Port configuration 507
- Figure 97 508
- Figure 98 510
- Cabling to the data equipment 510
- Figure 99 511
- RJ-11 or RJ-45 jacks 511
- Figure 100 512
- Patch panel layout 512
- 553-5022 513
- DAC administration (LD 11) 517
- (<CR>) 518
- Upgrading systems 522
- 553-AAA113 523
- 553-6160 529
- Card lock latch 529
- Figure 105 531
- NTDK16 Digital Line card 532
- Digital line interfaces 532
- Figure 106 533
- NTDK16 DLC 533
- 553-6161 542
- NT8D03 Analog Line card 545
- Line card 547
- 553-6165 550
- 553-6168 552
- Line interface units 553
- 553-AAA1131 560
- 553-6166 563
- Figure 113 569
- Note 1: 574
- Note 2: 574
- Note 3: 574
- Figure 116 575
- Administration program LD 14 576
- Figure 118 577
- Ground start operation 578
- CO / FX / WATS (far) end 579
- Figure 120 580
- Figure 122 583
- Direct inward dial operation 584
- CO (far) end 585
- Figure 124 586
- Figure 125 587
- RemarksSignal/direction 588
- 553-AAA1140 588
- Figure 127 590
- 553-AAA1142 591
- Figure 129 592
- Figure 131 595
- Figure 132 596
- Figure 134 599
- Figure 135 600
- Figure 136 601
- Figure 137 602
- Figure 138 604
- RTYP = MLSS 606
- Release control 611
- PAD switching 611
- Service change entries 619
- Figure 141 625
- Figure 142 630
- Figure 143 632
- Trunk circuit features 634
- Figure 144 635
- E&M Type I signaling 635
- Figure 145 636
- E&M Type II signaling 636
- Figure 146 637
- 4-wire DX signaling 637
- Figure 147 638
- Paging trunk operation 638
- Signaling interface 640
- Figure 148 642
- 553-6263 643
- Outgoing calls from near end 643
- Incoming calls to near end 643
- Note: 644
- 553-AAA1153 647
- 553-AAA1155 657
- Figure 154 659
- 553-6200 659
- Software service entries 661
- Figure 155 663
- Pad orientation 663
- Figure 156 666
- Paddle Board 667
- Figure 157 669
- NT8D41AA SDI paddle board 669
- Option switch settings 673
- DTE/DCE/Fiber mode 674
- Figure 159 676
- 553-5988 676
- Software service changes 677
- Equipment identification 679
- 553-8009 683
- System considerations 684
- Address 688
- (Part 2 of 2) 688
- NTAG26 XMFR card 695
- XMFR receiver specifications 697
- NTAK02 SDI/DCH card 701
- DCH function in the U.K 702
- Connecting to the ports 704
- NTAK09 1.5 Mb DTI/PRI card 709
- NTAK20 power on self-test 712
- NTAK93 self-test 713
- DTI/PRI local self-test 713
- Digital pad 716
- D-channel interface 717
- DS-1 Carrier interface 717
- Clock controller interface 719
- Clock rate converter 719
- NTAK10 2.0 Mb DTI card 721
- Carrier interface 728
- Switch settings 733
- Clocking modes 737
- Digital to analog converter 741
- CPU-MUX bus interface 742
- Signal conditioning 742
- Sanity timer 742
- Microprocessor 742
- External timing interface 743
- NTAK79 2.0 Mb PRI card 745
- NTAK79 switches 748
- 553-7869.EPS 749
- Switch 1 749
- Switch 3 749
- Switch 4Switch 2 749
- PAD SET 0 PAD SET 1 753
- PAD Offset PA D 753
- Carrier grounding 755
- CEPT transceiver 756
- Slip control 756
- D-channel support interface 756
- Card-LAN interface 758
- NTAK93 D-channel Handler 763
- Interface daughterboard 763
- D-Port — SDTI/PRI interface 767
- NTBK22 MISP card 769
- CPU to MISP bus interface 771
- MISP network bus interface 771
- Power consumption 771
- NTBK50 2.0 Mb PRI card 773
- 553-CSE7872 775
- Handler daughterboard 785
- Download operation 789
- Card reset 790
- Background audit 790
- Figure 167 798
- Figure 168 799
- Figure 169 800
- Route Data Block 801
- Trunk Data Block 802
- Prompt Response Description 806
- Busy tone detect 808
- Loss switching 808
- Trunk to Trunk connection 810
- Call disconnect 810
- Controller card 811
- Figure 170 813
- NTTK25 daughterboard 814
- 100BaseT IP daughterboards 815
- PC card interface 818
- Security device 819
- SDI ports 820
- Conferencing 820
- * Not supported 822
- Media Gateway 1000 823
- Figure 175 824
- MG 1000S Expansion slots 824
- NTRB21 DTI/PRI/DCH TMDI card 825
- Figure 176 827
- Figure 177 829
- NTRB21 TMDI card faceplate 829
- Software description 831
- Hardware description 831
- NTVQ01xx Media Card 839
- Figure 179 840
- Hardware architecture 841
- NTVQ01AA 842
- 553-MIRAN0001 842
- Survivability 843
- NTVQ55AA ITG Pentium card 845
- 553-CSE9150 847
- Backplane interfaces 848
- Assembly description 849
- Interface card 851
- Figure 182 853
- CPC513 ESDI card front panel 853
- Synchronous communication 855
- Clock timing option 856
- Test and maintenance features 856
- Connection characteristics 857
- Figure 184 858
- Configuring the ESDI card 862
- DTE/DCE mode jumper settings 863
- Figure 185 864
- 553-5983 864
- Figure 187 871
- QPC841 QSDI card front panel 871
- Figure 188 873
- Configuring the QSDI card 876
- Baud rate switch settings 878
- Figure 189 880
- Figure 190 883
- QPC841 QSDI card cabling 883
- The TDS/DTR card 885
- Tones and cadences 887
- Frame structure 902
- Commands and responses 904
- Description of procedure 905
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